The present disclosure relates to memory devices. More particularly, the disclosure relates to magnetic memory devices that have relatively small areas.
Magnetic memory such as magnetic random access memory (MRAM) is a non-volatile, semiconductor-based memory technology in which magnetic, rather than electrical, charges are used to store bits of data. In addition to offering non-volatility, magnetic memory devices are very fast and consume little power.
An example of a known magnetic memory device 100 is illustrated in FIG. 1. As shown in this figure, the magnetic memory device 100 comprises a plurality of memory cells or bits 102 that are arranged in a two-dimensional array. A relatively small number of these memory cells 102 have been depicted in FIG. 1 for purposes of explanation. Normally, the magnetic memory device 100 comprises many more such cells 102. For instance, the device 100 may comprise a 1024xc3x971024 array of memory cells 102. Each memory cell 102 is configured to store a single bit of information, i.e., a logic value xe2x80x9c1xe2x80x9d or a logic value xe2x80x9c0.xe2x80x9d
As is further illustrated in FIG. 1, the magnetic memory device 100 also comprises a plurality of column conductors 104 and row conductors 106 that are electrically coupled to the memory cells 102. Specifically, each memory cell 102 is connected to a column conductor 104 and a row conductor 106 at a cross-point of the conductors. Additionally, the magnetic memory device 100 includes column and row control circuits 108 and 110 which control switching for the various column and row conductors 104 and 106, respectively.
FIG. 2 provides a detailed view of a single memory cell 102 and its connection to its associated column and row conductor 104 and 106. As is evident from FIG. 2, each memory cell 102 typically comprises two magnetic layers 200 and 202 that are separated by a thin insulating layer 204. One of the magnetic layers (e.g., the bottom magnetic layer 202) has a fixed magnetic orientation, while the other magnetic layer (e.g., the top magnetic layer 200) has a xe2x80x9cfreexe2x80x9d magnetic orientation that can be relatively easily toggled from an orientation in which it aligns with the orientation of the fixed magnetic layer to an orientation in which it opposes the orientation of the fixed magnetic layer. The first state (aligned) of the memory cell 102 is called the xe2x80x9cparallelxe2x80x9d state and the second state (opposed) is called the xe2x80x9canti-parallelxe2x80x9d state.
The two different memory cell states can be used to record data due to their disparate effect on resistance of the memory cell 102. Specifically, the memory cell 102 has a relatively small resistance when in the parallel state, but has a relatively high resistance when in the anti-parallel state. By way of example, the parallel state can be designated as representing a logic value xe2x80x9c1xe2x80x9d while the anti-parallel state can be designated as representing a logic value xe2x80x9c0.xe2x80x9d In such a scheme, the magnetic memory device 100 can be written by changing the magnetic orientation of the free magnetic layer 200 of selected memory cells 102.
The control circuits 108 and 110 are used to facilitate selection of any given memory cell 102 during reading and writing. Normally, these circuits 108, 110 include a plurality of switches, for instance transistors, that are used to apply voltage to or provide current flow through selected conductors. FIG. 3 illustrates a switching arrangement 300 for a magnetic memory device of the type described above in relation to FIGS. 1 and 2. As indicated in FIG. 3, the memory cells are represented as resistors 302 that are electrically coupled to column conductors 304 and row conductors 306. At both ends of each conductor 304, 306 is a read/write transistor 308 that is used to select the various memory cells 302 during reading and writing.
To write data to a memory cell 302, current flow is provided through the column conductor 304 and row conductor 306 associated with a particular memory cell. For instance, if it is desired to write to the upper left memory cell 302 illustrated in FIG. 3, a current is provided to the leftmost column conductor 304 and the topmost row conductor 306 simultaneously. By way of example, the flow of current through the conductors is facilitated by providing a write voltage, VWR, to one end of each of the conductors and connecting the opposite end of each conductor to ground via the transistors 308. The magnetic fields created by the flow of electrons through the conductors 304 and 306 cause the orientation of the free layer (e.g., layer 200 in FIG. 2) of the memory cell 302 to change to, therefore, change the state of the cell.
Under one example reading scheme, the conductors 304, 306 associated with each unselected memory cell 302 are provided with a reference voltage, VA, and, simultaneously, one of the conductors associated with a selected memory cell 302 is connected to ground while the other associated conductor is provided with a read voltage, VAxe2x80x2, which has a magnitude similar to the reference voltage, VA With this configuration, current flows through the selected memory cell 302, and the resistance of the cell can then be determined to, thereby, determine the logic value stored by the cell.
As can be appreciated from the above discussion, a large number of transistors are needed to provide memory cell selectivity in known magnetic memory devices. Specifically, two transistors are needed for each column and row conductor of the device. Stated in another way, 2n transistors are needed for every n conductors in a given layer of the magnetic memory device. In that the conductors in known magnetic memory devices are electrically coupled to the memory cells, the voltage provided to the conductors during writing must be kept relatively low to avoid voltage breakdown of the memory cells. For instance, the voltage across any memory cell cannot exceed approximately 1 volt. In order to limit the voltage across the memory cells, the transistors must be relatively large, for example 100 times larger than that would be necessary if the transistor where only used for reading. Accordingly, known magnetic memory devices require a large number of relatively large transistors. Provision of these transistors increases the amount, i.e. area, of semiconductor material (e.g., silicon) required to fabricate the magnetic memory device and, therefore, significantly increases fabrication costs.
From the above, it can be appreciated that it would be desired to have magnetic memory devices that include control circuitry that requires less area to, thereby, reduce the area required by the magnetic memory devices.
The present disclosure relates to a magnetic memory device. In one embodiment, the magnetic memory device comprises a plurality of memory cells and a plurality of write conductors adjacent the memory cells but electrically isolated from the memory cells, at least two of the write conductors being connected to a single shared switch, wherein the write conductors are configured to provide a path for current to flow to thereby generate magnetic fields used to change a state of the memory cells.
The present disclosure further relates to a method for writing data to a memory cell of a magnetic memory device. In one embodiment, the method comprises providing a write voltage to a first end of a write conductor of the magnetic memory device with a first transistor, the write conductor being electrically isolated from the memory cell, connecting a second end of the write conductor to ground with a second transistor that is connected to at least one other write conductor of the magnetic memory device to create a first current path and a first magnetic field, and providing a write voltage to a separate conductor also connected to ground to create a second current path and a second magnetic field, wherein the first and second fields together change a state of the memory cell.